Vertical-cavity surface-emitting lasers (VCSELs) are good candidates for optical signal processing and optical buffer memories in photonic networks.^[1–3] Because of the circular transverse geometry, VCSELs can emit two orthogonal polarization lights, x-polarization and y-polarization (with the polarized direction along one of the two orthogonal directions associated with the crystalline or stress orientations, referred to as x and y directions). The polarization switching (PS) or the polarization bistability (PB) can be induced by varying the pump current, or by changing the injected power, or by varying the detuning of the injected light.^[2–15] Currently, these phenomena are generalized to apply into some areas of great concern, such as the optical logic devices and the storage installations of optical logic signals.^[2–7] It is very attractive that the logic devices and the storage ones can be implemented based on the PS or the PB of the optically injected VCSEL.

Several researches have been devoted to exploring logic gates by using the chatoic synchronization of semiconductor lasers^[16,17] and the PS or the PB of the VCSEL.^[5–7] In 2013, based on a master-slave-response synchronization system of chaotic multiple-quantum-well lasers, Yan et al. presented all-optical XNOR, NOR, NOT logic gates and their logic computational methods.^[16] They went on to implement optoelectronic NOR and XNOR logic gates using parallel synchronization of three chaotic lasers.^[17] Recently, Masoller and his co-workers have explored different types of optoelectric logic gates and all-optical ones using the PS or the PB of the optically injected VCSEL in different setups.^[5–7] However, in the setups presented in Refs. [5]–[7], the slight variations of some key parameters, such as the pump current, the optical injection strength, and the detuning of the injected light, can induce the change of the output polarization state.^{[8–15,18–31]} So the basic logic gates implemented in those setups have poor stability due to the instability of the PS. In Ref. [19], we put forward a scheme to control the PS in an optically injected VCSEL using electro-optic (EO) modulation, where the PS can be stably controlled if the applied electric field is fixed at a certain value. Based on the results presented in Ref. [19], with the logic inputs encoded in a modulation of the pump current, we implemented different types of optoelectric logic gates by controlling the logic operation of the applied electric field between the two logic input signals.^[4] In this paper, with the logic inputs encoded in the detuning of the injected light, we explore the implementations of different types of all-optical stochastic logic gates (NOT, OR, NOR, XOR, XNOR, AND, and NAND) in the VCSEL with tunable optical injection, controlling the logic signal of the applied electric field and using a new EO modulation theory. These all-optical logic gates can operate faster than the optoelectric composite ones given in Ref. [4].

The basic logic gates based on the optically injected VCSEL can be applied in combined logic photonic devices. However, they are difficult to apply in sequential logic photonic devices owing to the fact that their delay storages are not easy to realize. To solve this problem, in this paper, we further propose a novel method to perform the delay storages of the basic all-optical logic gates based on the theory of generalized chaotic synchronization in the cascaded VCSELs with optical injection. To quantify these observations, we also demonstrate their success probabilities as a function of the bit duration time of the logic input signal and the injection strength. Section 2 gives the schematic diagram of all-optical stochastic logic gates and their delay storages in the cascaded VCSELs with optical injection, and presents the corresponding theory model. Section 3 describes the calculated results for all-optical stochastic logic operations and their delay storages, and demonstrates the success probabilities computed with 90/10 and 80/20 criteria as a function of the injection strength and the duration of the bit.

So far, the response frequency of the VCSEL with 850 nm can be greater than 40 GHz,^[32] and its transmission rate has reached more than 10 GB/s. Besides, the modulation frequency of the EO modulator based on periodically poled LiNbO₃ (PPLN) crystal can match the response time of the VCSEL. On the basis of this consideration, we put forward a novel scheme for the implementations of all-optical logic gates, as shown in Fig. 1. Figures 1(a) and 1(b) show the functional modules and the corresponding light paths in detail, respectively. As seen from Fig. 1(a), the system has the following functions. The logic inputs are encoded in the frequency detuning of the injected light from a CW laser by the encode module. The logic outputs are decoded from the outputs x-polarization and y-polarization from the PPLN by using the decode module 1. The other logic ouputs are decoded from the two polarizations from the S-VCSEL output by the decode module 2. The EO modulator is used to modulate the light from the M-VCSEL output, where different logic outputs can be generated by controlling the logic operation of the applied electric field. In Fig. 1(b), the M-VCSEL is the master VCSEL subjected to the injection of the tunable light from the CW laser. The S-VCSEL is the slave VCSEL with the strong injecion of the delay light from the PPLN crystal output. The two VCSELs both have an operating wavelength of 850 nm and a threshold current of 6.8 mA. The optical isolator 1 (IS₁) ensures that the light of the CW laser is unidirectionally injected into the M-VCSEL. The IS₂ is used to avoid the light from the beam-splitter 1 (BS₁) feeding back into the M-VCSEL. The IS₃ ensures that the output light of the PPLN crystal unidirectionally propagates to the S-VCSEL. An optical variable attenuator (VA) is placed in the right side of the tunable CW laser to control the optical injection strength. An optical amplifier (OA) is placed in the left side of the S-VCSEL to enhance the strength of the injected light from the PPLN crystal. The applied electric field E₀ is along the x direction of the crystal coordinate system. Suppose that the light from the M-VCSEL propagates along the y direction in the PPLN crystal, the polar angle θ and the azimuth angle φ equal to π/2 and π/2, respectively. So, for the PPLN crystal with a uniaxial, the unit vector a of the o-light equals to (1, 0, 0) and the unit vector b of the e-light becomes (0, 0, 1). In this case, the o-light and the e-light are along the x direction and the z direction in the PPLN crystal, respectively. The basic ideas of the scheme are presented as follows. The tunable CW laser, as an edge emitting laser, emits the x-polarization light with different frequency. Based on this, the three detuning frequencies between the CW laser and the M-VCSEL are encoded into four logic input sets. The encoded x-polarization light is split into two beams by the BS₁. One of those is directly injected into the M-VCSEL. The other is first switched into the y-polarization light by the half wave plate 1 (HWP₁) and the HWP₂, and then injected into the M-VCSEL. In this case, according to the theory of the self-spin model,^[20,21] with a fixed injection current, the M-VCSEL simultaneously emits the x-polarizaion light and the y-polarization light, which are digital chaotic waves and separated by the PBS₁. The x-polarization from the PBS₁ is considered as the original input of the o-light in the crystal because it is along the polarized direction of the o-light. The y-polarization from the PBS₁ is set as the original input of the e-light when it is aligned with the polarized direction of the e-light (z-direction) by the Faraday rotator 1 (FR₁) and the HWP₃. Based on the couping-wave theory for a linear EO effect,^[33] the x-polarization and the y-polarization are subjected to EO amplitude modulation in the PPLN crystal. The output o-light with delay-time τ, from the PPLN crystal, as the x-polarization, is injected into the S-VCSEL by the PBS₃ and the OA; it is considered as the loigc output X₁. The output e-light with delay-time τ, as the y-polarization, is injected into the S-VCSEL when its polarized direction is aligned with the y-polarization by the HWP₂ and the FR₂. It is set as the logic output Y₁, and the X₁ is the NOT operation with the Y₁. The output x-polarization and y-polarization components from the S-VCSEL are, respectively, considered as the logic outputs X₂ and Y₂. By controlling the logic operation of the applied electric field between two logic inputs, some basic logic operations, such as NOT, OR, NOR, AND, NAND, XOR, and XNOR, can be performed in the outputs X₁ and Y₁. According to the theory of the generalized chaotic synchronization, with the S-VCSEL subjected to strongly injected light, the outputs X₂ and Y₂ are generally synchronized with the outputs X₁ and Y₁ with delay time, respectively. So it is prospective that the delay storages of some of the above-mentioned basic logic operations can be realized.

Fig. 1.

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Fig. 1. Schematic diagram of all-optical stochastic logic gates and their delay storages in the cascaded VCSELs with optical injection: (a) functional modules; (b) light paths in detail. M-VCSEL, master VCSEL; S-VCSEL, slave VCSEL; IS, isolator; PPLN, periodically poled LiNbO3; μM and μS, the normalization injection currents of the M-VCSEL and the S-VCSEL, respectively; BS, beam-splitter; PBS, polarization beam-splitter; TEF, transverse electric field; HWP, half wave plate; FR, Faraday rotator; M, mirror; VA, variable attenuator; OA, optical amplifier; the applied electric field E0 is a digital square wave; the logic outputs X1 and Y1 are decoded from the x- and y-polarization with the delay time τ and the scale factor from the PPLN crystal; and the logic outputs X2 and Y2 are decoded from the x- and y- polarization emitted by the S-VCSEL.

In the scheme presented in Fig. 1, the reliabilities of the logic operations depend on the stabilities of the polarization switchings or polarization bistability loops of the M-VCSEL and the PPLN crystal. From Refs. [5]–[7], it is known that the stability of the PS is heavily dependent on some key parameters, such as the injection current and the injection strengths of the x-polarization and the y-polarization in the M-VCSEL, the bit duration time of the logic input signals, and the detuning frequency of the injection field. It is well known that the stabilities of the injection current, the bit duration time, and the detuning frequency can be easily guaranteed in technology. But it is very difficult to ensure the stability of the injection strength of the x(y)-polarization, owing to the fact that it heavily depends on the optical properities of these passive optical components in the system, such as the polarization errors in the half-wave plates and the Faraday rotators, the isolation degrees of the optical isolators, the transmittivities and light splitting ratios of the beam splitters and the polarization beam splitters, the gain of the optical amplifier, the efficiency of EO modulation in the PPLN crystal, and so on. So in actual operations, the influence of the injection strength of the x(y)-polarization on the reliabilities of the logic operations is important (see Figs. 9 and 10 for details).

Using the well-known spin-flip model^[21] for a VCSEL operating in the fundamental transverse mode, extended to account for the external optical injection, we deduce the rate equations of the M-VCSEL in the frequency reference frame of the injected field as follows:^[7]

As shown in Fig. 1, the x-polarization is along the direction of the o-light from the PPLN crystal, and the y-polarization is aligned with the e-light by the FR₁ and the HWP₁. Under these conditions, the x-polarization and the y-polarization are considered as the original inputs of the o-light and the e-light, respectively. So we have

When the two polarization components subjected to EO modulation are first delayed by time τ, and then injected into the S-VCSEL, we have

In general, the optically injected VCSEL is composed of the tunable CW laser and the M-VCSEL, and its PS is detemined by Eqs. (1)–(4). Based on the PS, with the parameters μ_M and K_Mx (K_my) fixed at certain values, respectively, it can generate a logic output when the logic inputs are encoded from the detuning frequency of the injection field. According to the couping wave theory for a linear EO effect in the PPLN crystal described by Eqs. (6)–(11), the logic output of the optically injected VCSEL can be converted into another one by using different logic operations of the applied electric field between the two logic inputs. With the strong injection in the x(y)-polarization of the S-VCSEL, the x(y)-polarization from the S-VCSEL output, decribed by Eqs. (13)–(15), can be generally synchronized to that with delay time from the PPLN output. Based on this, it is possible that the loigc outputs are delay latched.

We first calculate Eqs. (1)–(3) and (13)–(15) using the fourth-order Runge–Kutta method. The parameters used for calculation are presented in Table 1, where n₁ and n₂ are from the Shellmerier refractive formula of the PPLN crystal.^[35] In addition, the values of some key parameters of the VCSEL are given as follows: μ_M = μ_S = 1.2; K_Mx = K_My = 10 ns⁻¹; K_Sx = K_Sy = 50K_Mx; E_inj = 0.6. With these parameters, the M-VCSEL and the S-VCSEL emit the y-polarization at the threshold currents, and display a sharp polarization switching to the orthogonal x polarization at about μ_M = μ_S = 1.8 (see Fig. 2). We consider μ_M = μ_S = 1.2 such that the M-VCSEL and the S-VCSEL emit the y-polarization in the following calculations.

Table 1.

Table 1.

Table 1. Parameters for all optical logic gate design. . Parameter and symbol Value Parameter and symbol Value line-width enhancement factor a 3 noise strength paranmeter D 106 field decay rate k 300 ns−1 polar angle θ π/2 spin relaxation γs 50 ns−1 azimuth φ π/2 nonradiative carrier relaxation rate γe 1 ns−1 crystal temperature F 293 K dichroism γa 2 ns−1 poled period of crystal Λ 5.8 × 105 m−1 birefringence γp 60 ns−1 duty ratio D 0.5 delay time τ 5 ns crystal length L 15 mm effective area of light spot SA 7.0686 μm2 refractive index of o-light n1 2.24 length of the laser cavity Lv 3 μm refractive index of e-light n2 2.17 effective refractive index of active layer ng 3.6 frequency detuning Δωs 0 rad/s volume of the active layer V 21.206 μm3 detuning ΔωI 150 rad· ns−1 entral of wavelength λ0 850 nm detuning ΔωII −65 rad· ns−1 field confinement factor to the active region Γ 0.5 detuning ΔωIII −280 rad· ns−1 threshold current of VCSEL Ith 6.8 mA duration of the bit T 10 ns differential material gain g 2.9 × 10−12 m3·s−1 slowly varing amplitude of the injected field Ainj 1.114 × 1010 m−3/2

Table 1. Parameters for all optical logic gate design. .

Fig. 2.

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	Fig. 2. Hysteresis cycles as a function of the normalized injection currents μM and μS, where μM = μS; Δω = −280 rad· ns−1; KMx = KMy = 10 ns−1; KSx = KSy = 50 ns−1; Einj = 0.6.

In our implementation of the all-optical stochastic logic gates using parallel optical injection (its definition is given in Refs. [4] and [19]) (see Fig. 1), we suppose that the detuning Δω equals to the sum of two square waves that encode the two logic inputs, Δω = dω₁ + dω₂. Here, the logic input for the detuning dω₁ is defined as A₁, and that for the detuning dω₂ is considered as the logic input A₂. In this case, there are four logic input sets: (0, 0), (0, 1), (1, 0), and (1, 1). Representing the (0, 1) and (1, 0) with the same detuning Δω_II, we can encode the four inputs with the three-level signals Δω_I, Δω_II, and Δω_III, where Δω_I (Δω_II − Δω_c) accounts for the set (0, 0), and Δω_III (Δω_II + Δω_c) represents the set (1, 1). But for the NOT gate design, the input is encoded in the detuning dω₁ of the injected field. The three-level signal used to vary Δω is constant during a time interval T, defined as the bit duration time. We suppose that A₁ = 1 when dω₁ = 75 rad· ns⁻¹, and A₁ = 0 if dω₁ = −140 rad· ns⁻¹. In the following calculation, Δω_II is set as −65 rad·ns⁻¹, and Δω_c is considered as 215 rad·ns⁻¹.

As shown in Fig. 1, it is known that, when the S-VCSEL is subjected to strong injection of the light from the PPLN crystal output, there appears the generalized chaotic synchronization between the x(y)-polarization emitted by the S-VCSEL and the x(y)-polarization with delay time τ and the scale factor from the PPLN output. To describe the synchronization quality of the two linear polarizations, we introduce correlation coefficients of the x-polariozation and y-polarization^[28] as follows:

Fig. 3.

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	Fig. 3. For the logic AND operation (see Fig. 8 and Table 4), the dependence of the correlation coefficients ρx and ρy on the injection strength KMx or KMy. Here, KMx = KMy; μM = μS = 1.2; KSx = KSy = 50 ns−1; Einj = 0.6, T = 10 ns.

Fig. 4.

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	Fig. 4. For different injection currents μM (μS), the bistabilities of the output x-polarizations ((a), (c)) and y-polarizations ((b), (d)) from the PPLN crystal and the S-VCSEL as a function of the detuning frequency between the CW laser and the M-VCSEL, Δω. The parameters are the same as those in Fig. 3.

Fig. 5.

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	Fig. 5. For different injection strengths KMx, the bistabilities of the output x-polarizations ((a), (c)) and y-polarizations ((b), (d)) from the PPLN crystal and the S-VCSEL as a function of the detuning frequency between the CW laser and the M-VCSEL, Δω. The parameters are the same as those in Fig. 3.

When equations (17) and (18) of the generalized chaotic synchronization are generalized to apply in the design of the logic gates, the delay storages of the all-optical logic gates can be performed. For this purpose, the x-polarization light and y-polarization light emitted by the S-VCSEL are set as two logic outputs X₂ and Y₂, respectively. The delay x(y)-polarization with the proportionality factor C₁ (C₂) from the PPLN crystal output is considered as the loigc output X₁ (Y₁). The decoding of the output responses are as follows: with only the x-polarization emitted by the S-VCSEL, X₂ = 1 and Y₂ = 0; if the S-VCSEL only emits the y-polarization, X₂ = 0 and Y₂ = 1; when the delay output from the PPLN is the x-polarization, X₁ = 1 and Y₁ = 0; with the delay output only being the y-polarization, X₁ = 0 and Y₁ = 1.

To design the all-optical logic gates, for different injection currents, we first calculate the dynamic evolutions of the bistabilities of the x-polarzations and the y-polarizations with the detunning frequency of the injection field, as shown in Fig. 4. Here, figures 4(a) and 4(c) show the bistabilities of the x-polarizations from the PPLN and the S-VCSEL output, respectively. Figures 4(b) and 4(d) display the bistabilities of the y-polarizations output from the PPLN and the S-VCSEL, respectively. From Fig. 4, it is found that the bistability loops of the x-polarization and the y-polarization from the PPLN are similar to those from the S-VCSEL when the injection current is fixed at a certain value owing to the generalized chaotic synchronization. With the injection current μ_M ranging from 1.2 to 1.4, two bistabilities appear in the x(y)-polarization. The width of the two bistabilities becomes broader with the further increase of the injection current. If the μ_M increases to 1.6, only a bistability exists in the x(y)-polarization. With it further increasing to 2, two bistabilities occur again in the x(y)-polarization, but the width of the two bistability loops appears to have large fluctuation. Besides, with the increase of μ_M, the bistabilities in the x(y)-polarization offset toward the larger postive detuning frequency. For different injection light strengths of the M-VCSEL, figure 5 further gives the dynamic evolutions of the bisabilities in the x(y)-polarization when μ_M = μ_S = 1.2. As seen from Fig. 5, with the injection strength K_Mx (K_My) increasing from 2 ns⁻¹ to 15 ns⁻¹, the widths of two bistabilities in the x-polarization and the y-polarization are further broadened. In the following, we demonstrate the implementation of the basic all-optical logic gates and their delay storages.

Under EO modulation in the PPLN crystal (see Fig. 1), the polarization switchings of the M-VCSEL and the S-VCSEL both appear to have a periodic oscillation with the increase of the applied field E₀.^[19] When E₀ is fixed at 85 kV/mm, the PS occurs. Therefore, E₀ = 0 kV/mm and E₀ = 85 kV/mm are used here to control the logic gates. By using the two values of E₀, the bistable hysteresis cycles Δare presented in Fig. 6 (Δω varies with a linear ramp in 3.2 μs). Figure 6 also shows the three values Δω_I, Δω_II, and Δω_III used for encoding the two logic inputs. As shown in Fig. 6, with the S-VCSEL subjected to the strong injection, the hysteresis cycles of the PPLN crystal output are basically similar to those of the S-VCSEL output owing to the high synchronization quality (see Fig. 3) when μ_M = μ_S = 1.2, K_Mx = K_My = 10 ns⁻¹, K_Sx = K_Sy = 50 ns⁻¹, E_inj = 0.6, which indicates that the logic outputs of the PPLN crystal can be latched by the strong optically injected S-VCSEL. With the applied electric field E₀ fixed at 0 kV/mm, under the condition of the constant injection E_inj = 0.6, for Δω = Δω_I and for Δω = Δω_III, the PPLN and the S-VCSEL both output the y-polarization. Δω_II is chosen in the center of the region where the x-polarization is on. When E₀ = 85 kV/mm, the outputs from the PPLN crystal and the S-VCSEL are both the x-polarization, with Δω = Δω_I and Δω = Δω_III. When Δω = Δω_II, the outputs are the y-polarization. In the following, we suppose that the logic symbol of E₀ is defined as e. For E₀ = 0 kV/mm, e = 0, and e = 1 if E₀ = 85 kV/mm.

Fig. 6.

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Fig. 6. Hysteresis cycles as a function of the detuning frequency between the CW laser and the M-VCSEL, Δω. Here, μM = μS = 1.2; KMx = KMy = 10 ns−1; KSx = KSy = 50 ns−1; Einj = 0.6, T = 10 ns. The red solid line indicates the intensity of the x-polarization, the blue dashed line is that of the y-polarization. Panels (a) and (b) show the hysteresis cycles from the PPLN crystal output when E0 = 0 kV/mm and E0 = 85 kV/mm, respectively. Panels (c) and (d) show the hysteresis cycles from the S-VCSEL output when E0 = 0 kV/mm and E0 = 85 kV/mm, respectively. The arrows indicate the three levels used to encode the logic inputs (see text for details).

Fig. 7.

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Fig. 7. The logic NOT, XNOR, and XOR operations and their delay storages, as well as time traces of the applied electric field, the x-polarization and the y-polarization from the S-VCSEL output, and the two polarizations with delay τ and scale factor from the PPLN output, where μM = μS = 1.2; KMx = KMy = 10 ns−1; KSx = KSy = 50 ns−1; Einj = 0.6; T = 10 ns. In panel (a), the reseda dashed line: the logic input signal dω2; the reseda solid line: the logic input signal dω1; the black solid line: the logic signal of the external electric field E0; the blue line: the y-polarization; the bottle green line: the x-polarization. In panel (b), E0 = 0 kV/mm; the red solid line indicates the three-level signal.

Table 2.

Table 2.

Table 2. Input–output combinations for the logic NOT gate when the logic signal e of the applied electric field is the same as that of the input A2, the logic input is encoded in the frequency detuning dω1; one logic output Y1 is decoded from the y-polarization with the delay τ and the scale factor from the PPLN crystal output; and the other logic output Y2 is decoded from the y-polarization emitted by the S-VCSEL. . Detuning dω1(A1) Detuning dω2(A2) Logic signal e Output with delay time τ and the scale factor from the PPLN Output of the S-VCSEL NOT gate: logic output Y1 NOT gate: logic output Y2 dω1L(0) dω2L(0) 0 y-polarization y-polarization 1 1 dω1H(1) dω2H(1) 1 x-polarization x-polarization 0 0

Table 2. Input–output combinations for the logic NOT gate when the logic signal e of the applied electric field is the same as that of the input A2, the logic input is encoded in the frequency detuning dω1; one logic output Y1 is decoded from the y-polarization with the delay τ and the scale factor from the PPLN crystal output; and the other logic output Y2 is decoded from the y-polarization emitted by the S-VCSEL. .

Table 3.

Table 3.

Table 3. Input–output combinations for the logic XNOR and XOR gates: the logic inputs are encoded in the frequency detuning of the injected light from the CW laser; the logic outputs X1 and Y1 are, respectively, decoded from the x-polarization and y-polarization with the delay τ and the scale factor from the PPLN crystal output. The logic outputs Y2 and X2 are decoded from the x-polarization and y-polarization emitted by the S-VCSEL, respectively. . Detuning Δω(A1, A2) Logic signal e Output with delay time τ and the scale factor from the PPLN XOR gate: logic output X1 XNOR gate: logic output Y1 Output of the S-VCSEL XOR gate: logic output X2 XNOR gate: logic output Y2 ΔωI(0, 0) 0 y-polarization 0 1 y-polarization 0 1 ΔωII(0,1) 0 x-polarization 1 0 x-polarization 1 0 ΔωII(1,0) 0 x-polarization 1 0 x-polarization 1 0 ΔωIII(1,1) 0 y-polarization 0 1 y-polarization 0 1

Table 3. Input–output combinations for the logic XNOR and XOR gates: the logic inputs are encoded in the frequency detuning of the injected light from the CW laser; the logic outputs X1 and Y1 are, respectively, decoded from the x-polarization and y-polarization with the delay τ and the scale factor from the PPLN crystal output. The logic outputs Y2 and X2 are decoded from the x-polarization and y-polarization emitted by the S-VCSEL, respectively. .

Fig. 8.

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Fig. 8. The logic AND, NAND, OR, and NOR operations and their delay storages, time traces of the applied electric field, the x-polarization and the y-polarization from the S-VCSEL output, and the two polarizations with dealy τ and the scale factor from the PPLN output, where μM = μS = 1.2; KMx = KMy = 10 ns−1; KSx = KSy = 50 ns−1; Einj = 0.6; T = 10 ns. Here, the red solid line: the three-level signal; the black solid line: the logic signal of the external electric field E0; the blue line: the output y-polarization; the bottle green line: the output x-polarization.

In Fig. 7, under different logic operations of E₀, we present the logic NOT, XNOR, and XOR operations, as well as their delay storages when Δω varies with a fast three-level signal. Table 2 gives the input–output combinations for the logic NOT gate. One sees from Fig. 7(a) and Table 1 that, with A₁ being 0 (1), the delay output of the PPLN is the y(x)-polarization, the logic output Y₁ equals to 1 (0) when the logic signals of E₀ are the same as the loigc input A₂. The logic output Y₂ has the same behavior as Y₁. As a result, Y₁ = A₁ and Y₂ = A₁. Figures 7(b) and 7(c) further display the logic operations and the delay storages of the logic XOR and XNOR gates, respectively, with the logic signal of the applied electric field being 0. Table 3 further gives the input–output combinations for them. From Figs. 7(b) and 7(c), and Table 3, it is found that, when (A₁, A₂) = (0, 0) and (A₁, A₂) = (1, 1), X₁ = 0 and Y₁ = 1, owing to the delay output from the PPLN being the y-polarization. X₂ = 0, Y₂ = 1 because the S-VCSEL emits the y-polarization. If (A₁, A₂) = (0, 1) and (A₁, A₂) = (1, 0), X₁ = 1 and Y₁ = 0, with the delay output being the x-polarization. X₂ = 1, Y₂ = 0, due to the output of the S-VCSEL being the x-polarization. So we have X₁ = A₁ ⊕ A₂ and X₂ = A₁ ⊕ A₂, as well as Y₁ = A₁ ⊙ A₂ and Y₂ = A₁⊙ A₂.

Under the logic operation of the applied electric field between A₁ and A₂, figure 8 shows the logic AND, NAND, OR, NOR operations and their delay storages, where μ_M = μ_S = 1.2; K_Mx = K_My = 10 ns⁻¹; K_Sx = K_Sy = 50 ns⁻¹; E_inj = 0.6. The input–output combinations for the logic AND and NAND gates are given in Table 4. Table 5 further provides those for the logic OR and NOR gates. From Figs. 8(a) and 8(b), and Table 4, one sees that the logic outputs have the following relations with two loigc inputs: X₁ = A₁ · A₂, X₂ = A₁ · A₂, Y₁ = A₁ A₂, and Y₂ = A₁ · A₂ when e = A₁ +A₂. As seen from Figs. 4(c) and 4(d), as well as Table 5, X₁ = A₁ + A₂, X₂ = A₁ +A₂, Y₁ = A₁ +A₂, and Y₂ = A₁ +A₂ while e = A₁· A₂.

Table 4.

Table 4.

Table 4. Input-output combinations for the logic AND and NAND gates under the logic operation of the applied electric field. . Detuning Δω(A1, A2) Logic signal e Output with delay time τ and the scale factor from the PPLN AND gate: logic output X1 NAND gate: logic output Y1 Output of the S-VCSEL AND gate: logic output X2 NAND gate: logic output Y2 ΔωI(0, 0) 0 y-polarization 0 1 y-polarization 0 1 ΔωII(0,1) 1 y-polarization 0 1 y-polarization 0 1 ΔωII(1,0) 1 y-polarization 0 1 y-polarization 0 1 ΔωIII(1,1) 1 x-polarization 1 0 x-polarization 1 0

Table 4. Input-output combinations for the logic AND and NAND gates under the logic operation of the applied electric field. .

Table 5.

Table 5.

Table 5. Input-output combinations for the logic OR and NOR gates under the logic operation of the applied electric field. . Detuning Δω(A1, A2) Logic signal e Output with delay time τ and the scale factor from the PPLN OR gate: logic output X1 NOR gate: logic output Y1 Output of the S-VCSEL OR gate: logic output X2 NOR gate: logic output Y2 ΔωI(0, 0) 0 y-polarization 0 1 y-polarization 0 1 ΔωII(0,1) 0 x-polarization 1 0 x-polarization 1 0 ΔωII(1,0) 0 x-polarization 1 0 x-polarization 1 0 ΔωIII(1,1) 1 x-polarization 1 0 x-polarization 1 0

Table 5. Input-output combinations for the logic OR and NOR gates under the logic operation of the applied electric field. .

The above analyses indicate that, with the same logic input signals, various digital optical-signal processings (NOT, XOR, XNOR, AND, NAND, OR, and XOR) can be implemented in the all-optical domain by controlling the logic opreration of the applied electric field. In particular, the delay storages of these basic logic gates can be implemented using the mechanism of the generalized synchronization. From Figs. 7 and 8, it is noted that the bit duration of the logic input signals is substantial in accordance with that of the logic output signals, i.e, the bit rates of the encoded signals are almost the same as those of the decoded signals.

To quantify the reliabilities of the logic gates from outputs X₁ and Y₁, as well as those from outputs X₂ and Y₂, in the following we calculate the success probability P (as the ratio between the number of correct bits to the total number of bits^[5]) using the same criteria as in Refs. [5]–[7]. The idea is to determine the logic output (1 or 0) by measuring only the intensity emitted in one polarization. We determine the logic outputs X₁ and X₂ in terms of the percentage of the light emitted in the two x-polarizations, repectively, from the delay output of the PPLN and the S-VCSEL output: when x is the correct polarization, the outputs X₁ and X₂ in a bit are considered as being correct if the percentage of light emitted in the x-polarization is above a certain value during the bit. Besides, according to the percentage of the light emitted in the two y-polarizations, we further determine the logic outputs Y₁ and Y₂: with y being the correct polarization, the outputs Y₁ and Y₂ are correct in a bit while the percentage of light emitted in the y-polarization exceeds a certain value. The following percentages are used: 90% and 80%. When x(y) is the “wrong” polarization, we consider that the logic outputs X₁ and X₂ (Y₁ and Y₂) in a bit are correct if a given percentage (say, 10% or 20%) or less of the emitted power is emitted in the x(y) polarization.^[5–7] For example, the most restrictive criterion (90/10) allows for up to 10% of the light to be emitted in the wrong polarization, and requires a minimum of 90% in the correct one.

Fig. 9.

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Fig. 9. Success probabilities computed with 90/10 and 80/20 criteria as a function of the injection strength KMx (KMy) in the x(y)-polarization, and the duration of the bit T. Here, μM = μS = 1.2; KMx = KMy; KSx = KSy = 50KMx; Einj = 0.6. (a) The logic outputs X1 and Y1; (b) the logic outputs X2 and Y2. The first and the third columns are for 90/10 criterion; and the second and the fourth columns are for 80/20 criterion. The first to seventh rows are in turn the logical NOT, AND, NAND, XOR, XNOR, OR, NOR.

From Refs. [5]–[7], it is known that the success probability P depends strongly on some key parameters, such as the bit duration time T, the noise strength, the pump current, the injection strength, and the detuning of the injected field. Limited by the article space, for the above-mentioned different logic gates, in this paper we only calculate the success probabilities with 90/10 and 80/20 criteria as a function of the injection strength K_Mx (K_My) in the x (y) polarization and the duration of the bit. The results are shown in Fig. 9, where μ_M = μ_S = 1.2; K_Mx = K_My; K_Sx = K_Sy = 50K_Mx; E_inj = 0.6. From this figure, it is found that P of each logic gate is basically the same using the same criterion. The range of the bit duration time where P = 1 for the 80/20 criterion is wider than that for the 90/10 one. To further describe the influence of the bit duration time T and the injection strength K_Mx (K_My) on the success probability, using the criteria 80/20 and 90/10, we take the logic AND operation as an example to analyse the dependence of the success probabilities on the K_Mx (K_My) for different T, as displayed in Fig. 10. From Figs. 9 and 10, one sees that, for the criterion 80/20 (see Fig. 10(a)), with T being 1 ns, the success probability P first decreases from 1 to 0.2823, then fluctuates between 0.2823 and 0.7645 when K_Mx increases from 1 ns⁻¹ to 20 ns⁻¹; if T = 3 ns, P decreases from 0.8 to 0.283, then increases to 0.7645 with the increase of K_Mx from 1 ns⁻¹ to 7.6 ns⁻¹. When K_Mx further increases to 19.2 ns⁻¹, P reaches 1; when T = 5 ns, the case of P = 1 occurs in the region of K_Mx from 10.8 ns⁻¹ and 20 ns⁻¹; if T ≥ 10 ns, P keeps 1 when K_Mx increases from 2.6 ns⁻¹ to 20 ns⁻¹. For the criterion 90/10 (see Fig. 10(b)), with the increase of K_Mx from 1 ns⁻¹ to 20 ns⁻¹, P first decreases from 0.8 to 0.0811, then fluctuates between 0.0811 and 0.5946 when T is fixed at 1 ns; if T further increases to 5 ns, P first decreases from 0.4432 to 0.2811, then increases to 0.7622; with T being 10 ns, P increases from 0.4432 to 0.7662 when K_Mx increases from 1 ns⁻¹ to 2.6 ns⁻¹, then remains the same with K_Mx increasing from 2.6 ns⁻¹ to 5.8 ns⁻¹. If K_Mx increases from 5.8 ns⁻¹ to 11 ns⁻¹, it is with oscillation and increases to 1. With K_Mx further increased from 11 ns⁻¹ to 20 ns⁻¹, it maintains a constant 1; with the increase of T to 15 ns, the case of P = 1 occurs in the region of K_Mx between 3.4 ns⁻¹ and 20 ns⁻¹; if T ≥ 16 ns, it keeps 1 when K_Mx is between 2.6 ns⁻¹ and 20 ns⁻¹.

Fig. 10.

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	Fig. 10. For different bit duration time T, the dependence of success probabilities on the injection strength KMx (KMy) with two different criterions for the logic AND operation, where (a): 80/20; (b): 90/10. The other parameters are the same as those in Fig. 9.

According to the above analyses, it is concluded that a P of no more than 0.8 can be obtained when the injection strengths k_Mx and k_My vary from 1 ns⁻¹ to 2.6 ns⁻¹. For the smaller bit duration time T, the case of P = 1 occurs at the larger injection strength. For stricter 90/10 criterion, with T being no less than 5 ns, the case of P no less than 0.7622 occurs in the region of the injection strength between 9 ns⁻¹ and 20 ns⁻¹. It is noted that with the injection strength of 10 ns⁻¹ and the bit duration time of 10 ns, given in Figs. 7 and 8, we obtain P = 1 for the 80/20 criterion in the logic outputs X₁, X₂, Y₁, and Y₂. Even with the stricter 90/10 criterion, it is more than 0.886. This further indicates that the reliable logic NOT, AND, XOR, XNOR, OR, and NOR gates can be performed by controlling the logic operation of the applied electric field, and successfully being latched by the generalized synchronization.

Based on the cascaded VCSELs subjected to optical injection, we put forward a novel implementation scheme for all-optical stochastic logic gates by using the dynamical properties of the polarization bistability, depending on the detuning of the injected light. We here consider that two logic inputs are encoded in the detuning of the injected light from a tunable CW laser, and the two logic outputs are decoded from the polarization state of the output light from the PPLN crystal. The two other logic outputs are decoded from that of the S-VCSEL output. By using differernt logic signals of the applied electric field, the reliable logic operations NOT, AND, NAND, XOR, XNOR, OR, and XNOR can be obtained under EO modulation. Specifically, based on the theory of the generalized chaotic synchronization, the delay storages of the above-mentioned logic gates can be successfully implemented. Even with stricter 90/10 criterion, these latched logic gates have quite high success probability (no less than 0.886) with the bit duration time of no less than 10 ns and the injection strength of more than 10 ns⁻¹. The operation time of this all-optical configuration is faster than that of the electro-optical implementation presented in Ref. [4]. It is noted that the all-optical configuration can be further generalized to apply in sequential logic photonic devices.